In semiconductor devices, for example, element units each including a wiring board and a semiconductor element mounted thereon are laminated, and the wiring boards are interconnected by connecting terminals. This well-known mounting method includes, for example, so-called package-on-package (PoP). In the semiconductor devices formed by the PoP method, semiconductor packages each including wiring boards such as package substrates and semiconductor elements (chips) mounted thereon are laminated, and the wiring boards are interconnected by bumps and the like.
Well-known methods of mounting semiconductor elements on wiring boards include, for example, wire connection and flip-chip bonding. Among these, flip-chip bonding may be carried out by, for example, placing a resin layer together with bumps between a semiconductor element and a wiring board, and by melting the bumps and the resin layer. In addition, a semiconductor element may be mounted on a wiring board by connecting bumps deposited on the semiconductor element to columnar electrodes formed on the wiring board (see, for example, Japanese Patent Nos. 3239909 and 4337949 and Japanese Laid-open Patent Publication Nos. 2010-080609 and 2000-260817).
In the semiconductor devices formed by the above-described PoP method, connection failure may occur when the lower and upper semiconductor packages interfere with each other. For example, if a resin layer that seals the semiconductor element of the lower semiconductor package interferes with the wiring board of the upper semiconductor package, connecting terminals such as bumps deposited on the upper wiring board may not be connected to pads on the lower wiring board.
In order to interconnect the lower and upper semiconductor packages using connecting portions including the connecting terminals without such interference between the semiconductor packages, for example, the positions of the pads on the lower wiring board may be raised, or additional electrodes may be provided for the pads. However, either method may lead to an increase in cost. In addition, even when the semiconductor packages are interconnected by the connecting portions, some semiconductor devices in known mounting forms have gaps left between the lower and upper semiconductor packages, and therefore do not have sufficient impact resistance and connection reliability.